Advantech PCI-1718 Manuel d'utilisateur Page 37
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- Table des matières
- MARQUE LIVRES
Noté. / 5. Basé sur avis des utilisateurs
29 Chapter 3
3.3.1 I/O Connector Signal Description
Table 3.9: I/O Connector Signal Descriptions
Signal
Name
Refere
nce
Direct
ion
Description
A/D S
<0..15>
A.GND Input
Analog input (single-ended), channels 0
through 15.
A/D H
<0..7>
A.GND Input
Analog input high (differential), channels 0
through 7.
A/D L
<0..7>
A.GND Input
Analog input low (differential), channels 0
through 7.
D/A A.GND Output Analog output
AGND - -
Analog Ground. The two ground references
(A.GND and D.GND) are connected together
on the PCI-1718HDU/HGU card.
D/O D.GND Output Digital output, channels 0 through 15.
D/I D.GND Input Digital input, channels 0 through 15.
CLK D.GND Input Clock input for the 8254.
GATE D.GND Input Gate input for the 8254.
OUT D.GND Output Signal output for the 8254.
VREF D.GND Output Voltage reference.
REFIN D.GND Input External voltage reference input.
S1-S4 D.GND Output Daughterboard channel select.
DGND - -
Digital Ground. The two ground references
(A.GND and D.GND) are connected together
on the PCI-1718HDU/HGU card.
+12V D.GND Output
+12 VDC Source (from ISA bus directly with
FUSE protection).
+5V D.GND Output
+5 VDC Source (from ISA bus directly with
FUSE protection).
NC - - No connection.
- PCI-1718 Series 1
- User Manual 1
- Contents 5
- Introduction 9
- Chapter 1 Introduction 10
- 1.1 Features 11
- 1.2 Applications 12
- 1.3 Installation Guide 13
- PCI-1718 Series User Manual 6 14
- 1.4 Software Overview 15
- PCI-1718 Series User Manual 8 16
- 9 Chapter 1 17
- 1.6 Accessories 18
- Installation 19
- Chapter 2 Installation 20
- 2.2 Driver Installation 21
- 2.3 Hardware Installation 23
- 17 Chapter 2 25
- Signal Connections 27
- Chapter 3 Signal Connections 28
- 23 Chapter 3 31
- Jumper Function description 31
- JP10 5 V (default) 31
- JP8 1 MHz (default) 32
- 27 Chapter 3 35
- Reset status after hot reset 35
- (default) 35
- 3.3 Signal Connections 36
- 31 Chapter 3 39
- 33 Chapter 3 41
- 35 Chapter 3 43
- Programming Guide 45
- Chapter 4 Programming Guide 46
- 39 Chapter 4 47
- 41 Chapter 4 49
- 43 Chapter 4 51
- 45 Chapter 4 53
- 47 Chapter 4 55
- 49 Chapter 4 57
- Specifications 59
- Appendix A Specifications 60
- A.2 Analog Output 61
- A.3 Digital Input 61
- A.4 Digital Output 62
- A.5 Counter/Timer 62
- A.6 General 63
- Block Diagrams 65
- Appendix B Block Diagrams 66
- Register Structure & 67
- C.1 Overview 68
- C.2 I/O Port Address Map 68
- 65 Appendix C 73
- Write A/D range control 73
- Bit # 76543210 73
- BASE + 01H XXXXG3*G2*G1G0 73
- 67 Appendix C 75
- Bit # 7 6543210 75
- C.9 D/A Output — BASE+04/05H 77
- Write FIFO interrupt control 78
- Bit # 7 654321 0 78
- C.12 A/D Status — BASE+08H 79
- C.13 A/D Control — BASE+09H 81
- Write Timer/Counter enable 82
- BASE + 0AH TC1 TC0 82
- C.18 FIFO Status — BASE+19H 84
- C.19 FIFO Clear — BASE+19H 84
- 77 Appendix C 85
- 79 Appendix C 87
- Calibration 89
- Appendix D Calibration 90
- D.1 VR Assignment 91
- D.2 A/D Calibration 92
- D.3 D/A Calibration 93
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