Advantech PCL-818 Series Manuel d'utilisateur télécharger pdf (Page 69)

61 Appendix C

C.18 FIFO Status — BASE+19H

The register at BASE+19H clears the FIFO buffer and sets its empty flag

(EF). The FIFO status register, address BASE+19H, has flags which you

can read to determine the current state of the FIFO buffer, including full

flag, half-full flag, and empty flag.

Table C-17 Register for FIFO Status

EF FIFO empty flag

1 FIFO is empty

0 FIFO is not empty

HF FIFO half-full flag

1 FIFO is half-full or more than half-full

0 FIFO is less than half-full

FF FIFO full flag

1 FIFO is full

0 FIFO is not full

Read FIFO status

Bit # 7 6 5 4 3 2 1 0

BASE + 19H FF HF EF

Note: This register is not used for PCL-818L.

1 2 ... 64 65 66 67 68 69 70 71 72 73 74

PCL-818 Series 1
User Manual 1
PCL-818 Series User Manual ii 2
PCL-818 Series User Manual iv 4
PCL-818 Series User Manual vi 6
Contents 7
Overview 9
Chapter 1 Overview 10
1.2 Features 11
1.3 Applications 12
1.4 Installation Guide 13
PCL-818 Series User Manual 6 14
1.5 Software Overview 15
1.6 Device Driver Roadmap 16
9 Chapter 1 17
1.7 Accessories 18
Installation 19
Chapter 2 Installation 20
2.2 Driver Installation 21
PCL-818 Series User Manual 14 22
2.3 Hardware Installation 23
PCL-818 Series User Manual 16 24
17 Chapter 2 25
Figure 2.5: Device Name 26
Figure 2.6: Test Utility 27
PCL-818 Series User Manual 20 28
Signal Connections 29
Chapter 3 Signal Connections 30
23 Chapter 3 31
PCL-818 Series User Manual 24 32
Switches Function Description 32
Jumpers Function Description 32
25 Chapter 3 33
JP11 External 33
Internal (default) 33
PCL-818 Series User Manual 28 36
Table 3-8: Jumper Settings 37
3.3 Signal Connections 38
31 Chapter 3 39
PCL-818 Series User Manual 32 40
33 Chapter 3 41
PCL-818 Series User Manual 34 42
35 Chapter 3 43
PCL-818 Series User Manual 36 44
Specifications 45
Appendix A Specifications 46
A.2 Analog Output 47
A.3 Digital Input /Output 47
A.4 Counter/Timer 48
A.5 General 48
Block Diagram 49
Appendix B Block Diagram 50
Register Structure & 51
C.1 Overview 52
C.2 I/O Port Address Map 52
Range codes appear below: 57
51 Appendix C 59
Bit # 7 6 5 4 3 2 1 0 59
C.9 D/A Output — BASE+04/05H 61
PCL-818 Series User Manual 54 62
Write FIFO interrupt control 62
Bit # 7 6543 2 1 0 62
BASE + 06H X X X X X X X FINT 62
C.12 A/D Status — BASE+08H 63
PCL-818 Series User Manual 56 64
C.13 A/D Control — BASE+09H 65
PCL-818 Series User Manual 58 66
Trigger Source ST1 ST0 66
Software trigger 0 X 66
External trigger 1 0 66
Pacer trigger 1 1 66
59 Appendix C 67
Write Timer/Counter enable 67
Bit # 7654321 0 67
BASE + 0AH TC1 TC0 67
C.18 FIFO Status — BASE+19H 69
C.19 FIFO Clear — BASE+19H 70
Calibration 71
Appendix D Calibration 72
D.1 VR Assignment 73
D.2 A/D Calibration 74
D.3 D/A Calibration 74

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Advantech PCL-818 Series Manuel d'utilisateur Page 69

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