Advantech PCI-1731 Spécifications télécharger pdf (Page 50)

APPENDIX C

PCI-1711/1731 User’s Manual

Advantech Co., Ltd.

www.advantech.com

– 46 –

Read Status Register

Bit # 7 6 5 4 3 2 1 0

BASE+7 IRQ F/F F/H F/E

BASE+6 CNT0 ONE/FH IRQEN GATE EXT PACER SW

C.8 Control Register — BASE+6

The write-only register BASE+6 allows users to set an A/D trigger

source and an interrupt source.

Table Control Register

SW Software trigger enable bit

1 enable; 0 disable.

PACER Pacer trigger enable bit

1 enable; 0 disable.

EXT External trigger enable bit

1 enable; 0 disable.

Note!

✎ Users cannot enable SW, PACER and EXT concurrently.

GATE External trigger gate function enable bit

1 enable; 0 disable.

IRQEN Interrupt enable bit

1 enable; 0 disable.

ONE/FH Interrupt source bit

0 interrupt when an A/D conversion occurs

1 interrupt when the FIFO is half full.

CNT0 Counter 0 clock source select bit

0 the clock source of Counter 0 comes from the

internal clock (1 MHz)

1 the clock source of Counter 0 comes from the

external clock (maximum up to 10 MHz).

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 59 60

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Advantech PCI-1731 Spécifications Page 50